CPU to Memory Interface, Static RAM, One two Dimensional Memory Cells, Matrix and Tree Decoders

<< NxN Crossbar Design for Barrel Rotator, IEEE Floating-Point, Addition, Subtraction, Multiplication, Division

Memory Modules, Read Only Memory, ROM, Cache >>

Advanced Computer Architecture-CS501

________________________________________________________

Advanced Computer Architecture

Lecture No. 37

Reading Material

Vincent P. Heuring & Harry F. Jordan

Chapter 7

Computer Systems Design and Architecture

7.1, 7.2

Summary

CPU to Memory Interface

Static RAM cell Organization and Operation

One & two Dimensional Memory Cells

Matrix and Tree Decoders

· Dynamic RAM

CPU to Memory Interface

The memory address register (MAR) is m-bits wide and contains memory address

generated by the CPU directly connected to the m-bit wide address bus. The memory

buffer register (MBR) is w-bit wide and contains a data word, directly connected to the

data bus which is b-bit wide. The register file is a collection of 32, 32-bit wide registers

used for data transfer between memory and the CPU. Memory address ranges from 0 to

2m-1.There also exist three control signals:

, REQUEST, and COMPLETE. When

signal is high, this would correspond to a read operation equivalent to having an

input data to the CPU and output from the memory. If this signal is low then it would be a

write operation and data would come from the CPU as an output and it would be written

into a portion in the memory. In this case, the REQUEST signal coming from the CPU

telling the memory that some interaction is required between the CPU and memory. As a

result of this request (either read/write), along with the signal on the control and the

address on the address bus, we might have the corresponding data on the data bus for a

read operation and after the operation is complete, the memory would issue a control

signal which corresponds in this case to COMPLETE.

Figure 7.1 of the text book.

Static RAM Cell Organization and Operation

A Typical Memory Cell

A memory cell provides four functions: Select, DataIn, DataOut, and Read/Write. DataIn

means input and DataOut means output. The select signal would be enabled to get an

operation of Read/Write from this cell.

Figure 7.3 of the text book.

1×8 Memory Cell Array (1D)

Page 344

Last Modified: 01-Nov-06

Advanced Computer Architecture-CS501

________________________________________________________

In this arrangement, each block is connected through a bi-directional data bus

implemented with 2 tri-state buffers.

and Select signals are common to all these

cells. This 1-dimentional memory array could not be very efficient, if we need to have a

very large memory.

4×8 Memory Cell Array (2D)

In this arrangement, 4×8 memory cell array is arranged in 2-dimensions. At the input, we

have a 2×4 decoder. Two address bits at the input A0 and A1 would be decoded into 4

signal specifies

select lines. The decoder selects one of four rows of cells and then

whether the row will be read or written.

A 64k×1 Static RAM Chip

The cell array is indicated as 256 × 256. So, there would be 256 rows and 256 columns.

A 64k × 1 cell array requires 16 address lines, a read/write line,

, a chip select line,

CS, and only a single data line. The lower order 8-address lines select one of the 256

rows using an 8-to-256 line row decoder. Thus the selected row contains 256 bits. The

higher order 8-address lines select one of those 256 bits. The 256 bits in the row selected

flow through a 256-to-1 line multiplexer on a read. On a memory write, the incoming bit

flows through a 1-to-256 line demultiplexer that selects the correct column of the 256

possible columns.

A 16k×4 Static RAM Chip

In this case, memory is arranged in the form of four 64×256 memory cells. Four bits can

be read and written at a time. For this, we use one 8-256 row decoder, four 64-1 muxes

and four 1-64 de muxes. The lower address lines (A0-A7) are decoded into 28 lines, 26

lines from these 28 are used to select row from one of the four 64×256 cell array and the

remaining 22 lines are used to select one of the 64×256 cell array. Now the upper address

lines (A8-A13) are input into the 4 muxes and their output is used to select the required

column from the four 64×256 cell arrays. Control lines read/write,

, chip select, CS,

are just similar to previous arrangement.

Matrix and Tree Decoders

A typical one level decoder has n inputs and 2n output, using one level of gates, each with

a fan-in of n. Two level decoders are limited in size because of high gate fan-in. In order

to reduce the gate fan-in to a value of 8 or 6, tree and matrix decoders are utilized.

Six Transistor SRAM Cell

In this arrangement, the cross connection is through inverters to make the latch, the basic

storage cell. This implementation uses six transistor cells. One transistor is used to

implement each of the two inverters, two transistors are used to control access to the

inverters for reading and writing, and two are used as active loads.

SRAM Read Operation

First of all, the CPU provides the address on the external address bus. The read/write

signal becomes active high. After time "tAA", the data becomes available on the data bus.

The chip retains this data on the data lines until the control signals are de asserted.

Page 345

Last Modified: 01-Nov-06

Advanced Computer Architecture-CS501

________________________________________________________

SRAM Write Operation

In the case of write cycle, the major difference is that along with the address the CPU has

also provided the data on the data bus. The chip select, CS, is immediately provided and

write signal is made low. The

line must be held valid for a minimum time interval

tw , the write time, until data, address, and control information have been propagated to

the cell and strobe into it. During this period the data lines must be driven with the data to

be written.

Dynamic RAM

As an alternate to the SRAM cell, the data can be stored in the form of a charge on a

capacitor (a charging/discharging transistor that can become a valid memory element),

and this type of memory is called dynamic memory. The capacitor has to be refreshed

and recharged to avoid data loss.

Dynamic RAM Cell Operation

In a DRAM cell, the storage capacitor will discharge in around 4-15ms. Refreshing the

capacitor by reading or sensing the value on bit line, amplifying it, and placing it back on

to the bit line is required. The need to refresh the DRAM cell complicates the DRAM

system design.

For details, refer to Chapter 7 of the text book.

Page 346

Last Modified: 01-Nov-06

Table of Contents: